Agenda

Dr. Jonathan Graf, CEO of Graf Research, will share how Graf Research is developing a new generation of configurable computing tools for electronic design automation and verification—tools that create independent, trustworthy views of FPGA configuration and silicon correctness.

Among these innovations is a method for bitstream equivalence checking, Enverite PV-Bit, which confirms whether an FPGA’s bitstream truly matches the intended gate-level netlist. Another is Ensofic, a silicon attestation platform that combines soft sensors with machine learning to evaluate both the reliability and authenticity of an FPGA, including the ability to spot counterfeit devices.

The talk will also cover what it takes to turn research prototypes into practical, commercial-grade solutions ready for deployment in high-stakes industries like aerospace, automotive, defense, and energy. Drawing on hands-on experience with deployed commercial solutions, Dr. Graf will outline key lessons learned and show how these projects have inspired unexpected new applications. The result is a clear picture of challenges and how the security of custom computing machines can advance rapidly in the years ahead.

Side-channel attacks using power- and EM-based methods have long been demonstrated in traditional ASIC systems. But, other physical side-channels have also played a role in reconfigurable hardware systems, including the detection of voltage changes in shared FPGA settings. Prior studies have proposed various malicious circuit designs that exploit combinations of traditional FPGA logic resources, i.e., Look-up Tables (LUTs), carry chains (CARRY), routing resources, and flip-flops (FFs). While bitstream checks have been added to the compiler and synthesis flows to mitigate these issues, there remain a number of additional resources of leakage that are an integral part of the FPGA, such as the DSP blocks used for complex mathematical operations, that, up to now, have not been exploited. In this talk, we will discuss two recent works that explain FPGA components as side channels. In the first work, LeakyDSP, I will discuss the use of DSP blocks to sense fine-grained voltage fluctuations, and in our other recent work, AmpereBleed, I will discuss how widely available sensors in ARM-FPGA SoCs can be used to exploit current-based side-channels. Taken together, this presentation aims to demonstrate that modern FPGA SoCs remain vulnerable to side-channel attacks, and that we need to continue to work to build new protections to prevent these recently discovered attacks.

Trevor E. Carlson is an Associate Professor at the department of Computer Science at the National University of Singapore. Prof. Carlson’s research interests include several areas of computer architecture including secure processor designs, highly efficient microarchitectures and accelerators, performance modeling and fast and scalable simulation methodologies. He co-designed the Sniper Multi-core Simulator which has been used by hundreds of researchers to evaluate the performance and power-efficiency of next generation systems and continues to be used to explore next-generation processor design. His processor and security works have been selected to appear in top computer architecture, security and design automation conferences (such as ASPLOS, DAC, ICCAD, ISCA, HPCA, MICRO, MICRO Top Picks, and USENIX Security). He has been awarded Amazon, Intel, Microsoft and VMWare Research Awards, and his work has received seven Best Paper Awards or Best Paper Nominations in conferences such as the International Symposium on Microarchitecture (MICRO), the Design Automation Conference (DAC), and the International Symposium on Performance Analysis of Systems and Software (ISPASS).

In this talk we will discuss some contributions to the security of processor-based systems in the context of embedded devices. We will discuss a solution to ensure constant-time computation and how the cache architecture can be extended to ensure constant-time properties. This approach exploits the software-hardware interface by extending ISA RISC-V to lock and unlock some sensitive data in the cache.

Guy Gogniat is Professor of ECE at the Université Bretagne Sud, Lorient, France, where he has been since 1998. In 2005, he spent a year as an invited researcher at the University of Massachusetts, Amherst, USA, working on the security of embedded systems using reconfigurable technologies. His work focuses on design methodologies and tools for embedded systems. He has conducted research in the area of reconfigurable and adaptive computing. He has been developing research in the area of embedded system security for 20 years. He is currently Vice-Dean of the Faculty of Sciences and the scientific and pedagogical director of the CYBERUS Erasmus Mundus programme in Cybersecurity.

We are moving to an era where quantum computing threatens the confidentiality of current cryptographic protocols, specifically around “harvest now, decrypt later” attacks. Algorithms such as CRYSTALS-Kyber and CRYSTALS-Dilithium, selected as NIST standards, are built on well-studied and mathematically robust foundations. However, strong algorithmic design alone is not enough. A cryptographic system remains vulnerable if the implementation is insecure—algorithmic security does not guarantee implementation security. We will see example on how Fault Injection could be still relevant for PQC.

Durga Ramachandran, Innovation Director at Keysight Technologies Riscure B.V. is currently leading the development of Post-Quantum Cryptography (PQC) solutions. She has 13 years of international experience across India, Singapore, UK, and the Netherlands. She gained technical background with Master’s in Electrical Engineering and business acumen from an MBA at Rotterdam School of Management.

Rapid advances in quantum computing hardware and software are bringing closer the promise of new discoveries and breakthroughs that these machines will enable. To fully utilize and trust quantum computers, however, users need assurances about the confidentiality and integrity of quantum circuits they execute on quantum computers. While existing research has begun to address the issues of quantum circuit confidentiality, there is lack of quantum computer architecture or hardware designs for ensuring and checking the integrity of quantum circuits. This gap in existing research and design of quantum computers is addressed in this talk. It outlines the design of CHEQ, our FPGA enabled Circuit Hashing Engine for Quantum controllers. By providing circuit integrity measurements to users through CHEQ, quantum computing systems can become more resilient to security threats that aim to attack circuit integrity. Combined with other prior work on confidentiality, the new CHEQ integrity assurance in quantum computers can enable complete circuit protection, and thus protection of future discoveries and breakthroughs generated by quantum computers.

Barbora Hrdá is a doctoral candidate at the Technical University of Munich and a research assistant at the Fraunhofer Institute for Applied and Integrated Security in Munich, Germany. She also collaborates with the Computer Architecture and Security Lab (CASLAB) led by Prof. Szefer at Northwestern University. The focus of her work at the Bavarian Competence Center for Quantum Security and Data Science includes security through, with and despite quantum computing. Her research focuses on methods that ensure the confidentiality and integrity of data processing on quantum computers and quantum computing platforms.

Neural networks have become the fundamental component of numerous practical applications. Implementations of neural networks, which are often accelerated by hardware, are integrated into all types of real-world physical devices. Substantial efforts have been made to uncover vulnerabilities and enhance privacy protection at the algorithmic level, but neural networks are ultimately implemented and deployed on physical devices. In this talk, we will take a look at recent advances and challenges in the physical side-channel analysis of neural network implementations.

Zhuoran Liu is a postdoctoral researcher in the CESCA Lab at Radboud University in the Netherlands. His research interests include adversarial machine learning, side-channel analysis, and physical security.

Masking has long been acknowledged as an effective and efficient protection against side-channel attacks. However, designing and implementing masked cryptographic hardware remains a challenging task, despite the numerous masking schemes proposed over the years. Achieving correct and efficient implementations typically requires extensive manual effort and deep expertise in both hardware design and physical security. Consequently, the development of masked hardware often proves to be highly complex and error-prone for engineers and practitioners. Without such expertise, designers may overlook subtle security flaws that could compromise the entire system and are difficult to detect through experimental analysis. This talk addresses these challenges by presenting automated procedures for the generation and evaluation of masked hardware. For the generation part, we leverage the concept of composable security, which involves combining small hardware gadgets that can be arbitrarily composed to form more complex secure circuits. Additionally, we explore recent challenges in the verification of masked circuits, including those that do not rely on composable gadgets.

Nicolai Müller is a PhD student and research assistant in the Implementation Security Group at Ruhr University Bochum, Germany. His research focuses on side channel, hardware, and implementation security, with a particular emphasis on automated applications to detect and mitigate flaws in masked circuits. He has authored several publications in top-tier venues, including IACR TCHES and ACM CCS. In 2022, he received first prize in the 9th German IT Security Award for his contribution to a toolbox for automated generation and evaluation of protected hardware.

To ensure that security is implemented in a sustainable way, it is necessary that the implemented primitives consume little resources and are supporting crypto-agility (so to allow updates of security primitives rather than replacement of whole system). In this talk, we will deep dive in the concept of crypto agility from a hardware point of view, explaining the considerations that should be made when designing crypto-agile hardware and discussing how FPGAs can help to provide cryptog-agility.

Dr. Francesco Regazzoni is Associate Professor at University of Amsterdam and also affiliated with Università della Svizzera italiana. His research interests are mainly focused on secure IoT devices and embedded systems, covering in particular design automation for security, physical attacks and countermeasures, post-quantum cryptography, and efficient implementation of cryptographic primitives. He is the coordinator of the SECURED Horizon Europe Project.

Modern vehicles integrate over 100 electronic control units (ECUs) to manage a wide spectrum of safety-critical and comfort-oriented functions. These systems increasingly rely on external connectivity—via V2X communication and over-the-air (OTA) updates—to enhance capabilities and maintain operational relevance. However, the convergence of software-defined functionality with legacy in-vehicle network architectures (e.g., CAN, LIN, FlexRay) and off-the-shelf hardware (embedded control units or ECUs) introduces significant attack vectors. Recent studies have demonstrated that adversaries can exploit these vulnerabilities to gain unauthorized access, inject malicious commands, and compromise core vehicular subsystems through relatively low-complexity network-based attacks. This underscores the urgent need for robust, in-vehicle security mechanisms that operate independently of the time- and safety-critical application on the ECUs. In this talk, we show a case for the integration of security primitives—specifically intrusion detection and prevention systems (IDPS)—directly within the network interface layer. By abstracting these functions below the application layer, we enable an ultra-low-latency threat mitigation and lay the groundwork for implementing security as a virtualized network function (VNF). This architectural shift is critical for building scalable, resilient, and secure vehicular communication frameworks in next-generation automotive platforms.

Dr. Shreejith Shanker is an Assistant Professor of Reconfigurable Computing at Trinity College Dublin, Ireland and leads the research group on reconfigurable computing systems. He is a member of the CONNECT research centre and the Sigmedia Group. His research interests include reconfigurable and adaptive computing systems, in-network computing, post-production media workflows, design automation tools and distributed embedded systems, with a focus on performance-energy trade-off and hardware-software codesign approaches.

European regulation is taking a leading role with respect to cyber security. This has resulted, for example, in the Cyber Resilience Act (CRA) and the NIS2 Directive. As is reflected in these initiatives, it is more important than ever to be informed on the “health status” of electronic devices. Attestation is a very useful technique that can help an operator and/or user to gain insights in the “health status” of their devices. Running attestation on software/firmware is a necessary but (possibly) insufficient measure. When targeting an FPGA, the configuration of the device can also be attested to a certain extent. This talk discusses how FPGA attestation can be achieved and touches on the challenges that occur while running attestation.

Jo Vliegen got his master’s degree in engineering technology in 2005 from the KHLim university college. After a little over three years, he returned to campus Diepenbeek and started working on FPGAs under the supervision of Nele Mentens. He obtained his PhD from KU Leuven in 2014 with a dissertation entitled: “Partial and dynamic FPGA reconfiguration for security applications” under the promotorship of prof. Ingrid Verbauwhede and prof. Nele Mentens. Jo was a post-doc in the COSIC and ES&S research groups between 2014 and 2020. From 2020 onwards he works as a research expert in both COSIC and ES&S. His research still focuses on FPGAs and their usage in security applications mainly targeting attestation through RISC-V.