The workshop will be organized as two 1.5-hour sessions. Each session will have a 20 minute mini-keynote, followed by 50 minutes of short presentations.

Session A

Time (PST) Title Presenter and Authors
9:00 Opening Notes Workshop Organizers
9:05 Getting Logical Security Right for Modern FPGAs – A Battle with Complexity Chandni Bhowmik and Sayak Ray
9:25 On-Chip Impedance Sensing for System-Level Tamper Detection Shahin Tajik, Tahoura Mosavirik, and Patrick Schaumont
9:35 Remote Power Attacks against Machine Learning Accelerators in Cloud FPGAs Shanquan Tian, Shayan Moini, Daniel Holcomb, Russell Tessier, and Jakub Szefer
9:45 Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs Ognjen Glamočanin, Hajira Bazaz, Mathias Payer, and Mirjana Stojilović
9:55 Pentimento: Data Residue in Digital Hardware Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, and Dustin Richmond
10:05 A Hardware/Software Framework for System-on-FPGA Security Sujan Saha Kuman, Kawser Ahmed, and Christophe Bobda
10:15 Discussion Session Workshop Organizers
10:30 Break Coffee and Tea

Session B

Time (PST)   Presenter and Authors
11:00 Introduction Workshop Organizers
11:05 Scalable Assurance via Verifiable Hardware-Software Contracts Caroline Trippel
11:25 Atoms and Bits of Edge Intelligence Ali Keshavarzi
11:35 Side-Channel Protected NNs Through Secure and Private Function Evaluation Fatemeh Ganji, Domenic Forte, Mohammad Hashemi and Steffi Roy
11:45 Cloning the Unclonable: Physically Cloning an FPGA RO PUF Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad Hutchings and Jeff Goeders
11:55 Revisiting RAM-Jam in the Face of Fault-Tolerant FSM Design and Layout Domenic Forte, Mahbub Alam, Muhtadi Choudhury, Fatemeh Ganji, and Shahin Tajik
12:05 Discussion Session Workshop Organizers
12:30 End of Workshop / Lunch