SCCM 2023

The 3rd Workshop on Security for Custom Computing Machines (SCCM) will be held in conjunction with FPGA 2023.

Hardware security is an important design consideration. Recent events have raised awareness of security in general-purpose processors. As experts we must consider: What are the equivalents for reconfigurable architectures and custom computing machines? How do we defend against threats that exist today? How do we design our systems to defend against future threats? This is increasingly important as we deploy customized hardware at unprecedented scales.

This workshop is an opportunity to publicize our field at a top-tier conference. Our goal is to increase the awareness of ongoing research in this area, develop new collaborations, and share research progress.

Date & Time

Sunday, Feb 12, 2023. 9:00am - 12:30pm PST.

Location

Monterey Marriott, room San Carlos III.

Registration

  • In-person: Register as part of FPGA 2023 and fill in the 2023 SCCM Registration form.
  • Virtual: Fill in the 2023 SCCM Registration form to receive the Zoom link by e-mail.

Organizers

Confirmed Speakers

  • Chandni Bhowmik (Intel) Getting Logical Security Right for Modern FPGAs – A Battle with Complexity
  • Caroline Trippel (Stanford), Scalable Assurance via Verifiable Hardware-Software Contracts
  • Ali Keshavarzi (Stanford), Atoms and Bits of Edge Intelligence
  • Fatemeh Ganji (WPI), Side-Channel Protected NNs Through Secure and Private Function Evaluation
  • Shahin Tajik (WPI), On-Chip Impedance Sensing for System-Level Tamper Detection
  • Domenic Forte (UF), Revisiting RAM-Jam in the Face of Fault-Tolerant FSM Design and Layout
  • Hayden Cook (BYU), Cloning the Unclonable: Physically Cloning an FPGA RO PUF
  • Colin Drewes (Stanford), Pentimento: Data Residue in Digital Hardware
  • Ognjen Glamočanin (EPFL), Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs
  • Shanquan Tian (Yale), Remote Power Attacks against Machine Learning Accelerators in Cloud FPGAs
  • Sujan Saha Kuman (UF), A Hardware/Software Framework for System-on-FPGA Security

Agenda

The workshop will be organized as two 1.5-hour sessions. Each session will have a 20 minute mini-keynote, followed by 50 minutes of short presentations.

Session A

Time (PST) Title Presenter and Authors
9:00 Opening Notes Workshop Organizers
9:05 Getting Logical Security Right for Modern FPGAs – A Battle with Complexity Chandni Bhowmik and Sayak Ray
9:25 On-Chip Impedance Sensing for System-Level Tamper Detection Shahin Tajik, Tahoura Mosavirik, and Patrick Schaumont
9:35 Remote Power Attacks against Machine Learning Accelerators in Cloud FPGAs Shanquan Tian, Shayan Moini, Daniel Holcomb, Russell Tessier, and Jakub Szefer
9:45 Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs Ognjen Glamočanin, Hajira Bazaz, Mathias Payer, and Mirjana Stojilović
9:55 Pentimento: Data Residue in Digital Hardware Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, and Dustin Richmond
10:05 A Hardware/Software Framework for System-on-FPGA Security Sujan Saha Kuman, Kawser Ahmed, and Christophe Bobda
10:15 Discussion Session Workshop Organizers
10:30 Break Coffee and Tea

Session B

Time (PST)   Presenter and Authors
11:00 Introduction Workshop Organizers
11:05 Scalable Assurance via Verifiable Hardware-Software Contracts Caroline Trippel
11:25 Atoms and Bits of Edge Intelligence Ali Keshavarzi
11:35 Side-Channel Protected NNs Through Secure and Private Function Evaluation Fatemeh Ganji, Domenic Forte, Mohammad Hashemi and Steffi Roy
11:45 Cloning the Unclonable: Physically Cloning an FPGA RO PUF Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad Hutchings and Jeff Goeders
11:55 Revisiting RAM-Jam in the Face of Fault-Tolerant FSM Design and Layout Domenic Forte, Mahbub Alam, Muhtadi Choudhury, Fatemeh Ganji, and Shahin Tajik
12:05 Discussion Session Workshop Organizers
12:30 End of Workshop / Lunch